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preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland 4 gb ddr2 C sdram registered s o - rdimm 200 pin s o - rdimm seg04g72b1bc2mt - 30 r 4 gb yte in fbga technology rohs compliant options: ? data rate / latency marking ddr2 667 mt/s cl5 - 30 ? module densities 4gb with 18 dies and 2 rank s ? standard grade (t a ) 0c to 70c (t c ) 0c to 85c environmental requirements: ? operating temperature (t c ) standard grade 0c to 85c ? operating humidity 10% to 90% relative humidity, noncondens ing ? operating pressure 105 to 69 kpa (up to 10000 ft.) ? storage temperature - 55c to 100c ? storage humidity 5% to 95% relative humidity, noncondensing ? storage pressure 1682 psi (up to 5000 ft.) at 50c figure: mechanical dimensions features: ? 200 - pin 72 - bit small outline registered dual - in - line double data rat e synchronous dram module ? module organization: dual rank 512mx72 ? v dd = 1.8v + 0.1v, v ddq = 1.8v + 0.1v ? 1.8v i/o ( sstl_18 compatible) ? serial presence detect with eeprom ? phase - lock loop (pll) clock driver to reduce loading ? supports ecc error detection and cor rection ? gold - contact pad ? this module family is fully pin and functional compatible to the jedec pc2 - 5300 spec. and jedec - standard mo 224. (see www.jedec.org ) ? the pcb and all components are manufactured according to th e rohs compliance specification [eu directive 2002/95/ec restriction of hazardous substances (rohs)] ? ddr2 sdram component micron mt47h256m8eb - 25e:c ? 256mx8 ddr2 sdram in fbga - 60 package ? four bit prefetch architecture ? programmable cas latency (cl) ? posted ca s additive latency (al) ? write latency = read latency C 1 t ck ? programmable burst length: 4 or 8 ? adjustable data - output drive strength ? on - die termination (odt) ? dll to align dq and dqs transitions with ck 1 the reference according mo224
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland this swissbit module is an industry standard 200 - pin 8 - byte ddr2 sdram small outline registered dual - in - line memory module (s o - rdimm) which is organized as x72 high speed cmos memory arrays. a register component and a pll chip reduce loading on the clock and command/address bus. the module uses ddr2 sdram devices with eight internal banks . the modul e uses double data rate to achieve high - speed operation. ddr2 sdram modules operate from a differential clock (ck and ck#). read and write accesses to a ddr2 sdram module is burst - oriented; accesses start at a selected location and continue for a programme d number of locations in a programmed sequence. the burst length is either four or eight locations. an auto precharge function can be enabled to provide a self - timed row precharge that is initiated at the end of a burst access. the ddr2 sdram devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. a self refresh mode is provided and a power - saving power - down mode. all inputs and all full drive - strength outputs are sstl_18 compatible. the ddr2 sdram module uses the serial presence detect (spd) function implemented via serial eeprom using the standard i 2 c protocol. this nonvolatile storage device contains 256 bytes. the first 128 bytes are utilized by the dimm manufacturer (swissbit) to identify the module type, the modules organization and several timing parameters. the second 128 bytes are available to the end user. module configuration organization ddr2 sdrams used row addr. device bank addr. col umn addr. refresh module bank select 512 m x 72 bit 18 x 256 m x 8bit ( 2048 m bit) 1 5 ba0, ba1, ba2 10 8k s0#, s1# module dimensions in mm 67.6 (long) x 30.0(high) x 3.80 [max] (thickness) timing parameters part number module density transfer rate clock cycle /data bit rate latency seg04g72b1bc2mt - 30 r 2 gb 5.3 gb/s 3.0 ns / 667 mt/s 5 - 5 - 5 pin name a0 - a1 4 address inputs ba0 C ba2 bank address inputs dq0 C dq63 data input / output cb0 C cb7 check bits dm0 - dm8 input data mask ras# row address strobe cas# column address strobe we# write enable cke 0 / cke1 clock enable ck0 clock input, positive line ck0# clock input, negative line dqs0 - dqs8 data strobe, positive line dqs0# - dqs8# data strobe, negative line (only used when differential data strobe mode is enabled) s0# / s1# chip select reset # asynchronously forces all registered outputs low when reset# is low. this signal can be used during power - up to ensure that cke is low and dqs are high - z. v dd supply voltage (1.8v 0.1v) figure 1: mecha nical dimensions
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland v ref input / output reference v ss ground v ddspd serial eeprom positive power supply scl serial clock for presence detect sda serial data out for presence detect sa0 C sa1 presence detect address inputs odt0 / odt1 on - die termination nc no connection pin configuration pin # front side pin # back side pin # front side pin # back side 1 v ref 2 v ss 101 v dd 102 a6 3 dq0 4 dq4 103 a5 104 a4 5 v ss 6 dq5 105 a3 106 v dd 7 dq1 8 v ss 107 a2 108 a1 9 dqs0# 10 dm0 109 v dd 110 a0 11 dqs0 12 v ss 111 a10 | ap 112 ba1 13 v ss 14 dq6 113 ba0 114 v dd 15 dq2 16 dq7 115 ras# 116 we# 17 dq3 18 v ss 117 v dd 118 s0# 19 v ss 20 dq12 119 cas# 120 odt0 21 dq8 22 dq13 121 s1# 122 a13 23 dq9 24 v ss 123 v dd 124 v dd 25 v ss 26 dm1 125 odt1 126 ck0 27 dqs1# 28 v ss 127 nc (s3#) 128 ck0# 29 dqs1 30 dq14 129 dq32 130 v ss 31 v ss 32 dq15 131 v ss 132 dq36 33 dq10 34 v ss 133 dq33 134 dq37 35 dq11 36 dq20 135 dqs4# 136 v ss 37 v ss 38 dq21 137 dqs4 138 dm4 39 dq16 40 v ss 139 v ss 140 v ss 41 dq17 42 reset # 141 dq34 142 dq38 43 v ss 44 dm2 143 dq35 144 dq39 45 dqs2# 46 v ss 145 v ss 146 v ss 47 dqs2 48 dq22 147 dq40 148 dq44 49 v ss 50 dq23 149 dq41 150 dq45 51 dq18 52 v ss 151 v ss 152 v ss 53 dq19 54 dq28 153 dqs5# 154 dm5 55 v ss 56 dq29 155 dqs5 156 v ss 57 dq24 58 v ss 157 v ss 158 dq46 59 dq25 60 dm3 159 dq42 160 dq47 61 v ss 62 v ss 1 61 dq43 162 v ss 63 dqs3# 64 dq30 163 v ss 164 dq52 pin # front side pin # back side pin # front side pin # back side
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland 65 dqs3 66 dq31 165 dq48 166 dq53 67 v ss 68 v ss 167 dq49 168 v ss 69 dq26 70 cb4 169 v ss 170 dm6 71 dq27 72 cb5 171 dqs6# 172 v ss 73 v ss 74 v ss 173 dqs6 174 dq54 75 cb0 76 dm8 175 v ss 176 dq55 77 cb1 78 v ss 177 dq50 178 v ss 79 v ss 80 cb6 179 dq51 180 dq60 81 dqs8# 82 cb7 181 v ss 182 dq61 83 dqs8 84 v ss 183 dq56 184 v ss 85 v ss 86 cb2 185 dq57 186 dm7 87 cke0 88 cb3 187 v ss 188 dq62 89 cke1 90 v ss 189 dqs7# 190 v ss 91 nc (s2#) 92 ba2 191 dqs7 192 dq63 93 v dd 94 a14 193 dq58 194 sda 95 a12 96 a11 195 v ss 196 scl 97 a9 98 v dd 197 dq59 198 sa1 99 a7 100 a8 199 v ddspd 200 sa0
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland functional block diagramm 2 gb ddr2 ecc registered sod imm, 2 rank s and 18 components
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland maximum electrical dc characteristics parameter/ condition symbol min max units supply voltage v dd - 1.0 2.3 v i/o supply voltage v dd q - 0.5 2.3 v v dd l supply voltage v dd l - 0.5 2.3 v voltage on any pin relative to v ss v in , v out - 0.5 2.3 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 40 40 ck, ck# - 20 20 dm - 5 5 output leakage curr ent (dqs and odt are disabled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 16 16 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.7 1.8 1.9 v i/o supply voltage v dd q 1.7 1.8 1.9 v v dd l supply voltage v dd l 1.7 1.8 1.9 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt v ref C ref v ref + 0.04 v input high (logic 1) voltage v ih (dc) v re f + 0.125 v dd q + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.25 - v input low (logic 0) voltage v il (ac) - v ref - 0.25 v capacitance at ddr2 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. simulations can then render a considerably more accurate result. jedec modules are now designed by using simulations to close timing budgets.
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland i dd specifications and conditions (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) parameter & test condition symbol max. unit 5300 - 555 operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between valid comma nds; dq inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 648 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t r c (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 696 ma precharge power - down current: all device banks idle; power - down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref i dd2p 192 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all control and addr ess bus inputs are not changing; dqs are floating at v ref i dd2q 672 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd2n 736 ma active power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast pdn exit mr[12] = 0 i dd3p 256 ma slo w pdn exit mr[12] = 1 256 active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two c lock cycles; dq inputs changing once per clock cycle i dd3n 800 ma operating read current: all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 1055 ma
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland parameter & test condition symbol max. unit 5300 - 555 oper ating write current: all device banks open, continuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4w 976 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid commands; all other control and addres s bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 2400 ma self refresh current: ck and ck# at 0v; cke 0.2v; all other control and address bus inputs are floating at v ref ; dqs are floating at v ref i dd 6 192 ma operating current*) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid comma nds; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 1536 ma *) value calculated as one module rank in this operating condition, and all other module ranks in idd2p (cke low) mode. timing values used fo r i dd measurement i dd measurement conditions symbol 5300 - 555 unit cl (i dd ) 5 t ck t rcd (i dd ) 15 ns t rc (i dd ) 60 ns t rrd (i dd ) 7.5 ns t ck (i dd ) 3.0 ns t ras min (i dd ) 45 ns t ras max (i dd ) 70 000 ns t rp (i dd ) 15 ns t rfc (i dd ) 105 ns
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland ddr 2 sdram component electrical characteristics and recommended ac operating conditions (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300 - 555 parameter symbol min max unit clock cycle time cl = 5 t ck (5) 3.0 8.0 ns cl = 4 t ck (4) 3.75 8.0 ns cl = 3 t ck (3) 5.0 8.0 ns ck high - level width t ch 0.45 0.55 t ck ck low - level width t cl 0.45 0.55 t ck half clock period t hp min (t ch, t cl ) ps access window (output) of dq s from ck/ck# t ac - 0.45 +0.45 ns data - out high - impedance window from ck/ck# t hz +0.45 (= t ac max ) ns data - out low - impedance window from ck/ck# t lz - 0.45 (= t ac min) +0.45 (= t ac max ) ns dq and dm input setup time relative to dqs t ds 0. 10 ns dq and dm input hold time relative to dqs t dh 0. 30 ns dq and dm input pulse width ( for each input ) t dipw 0.35 t ck data hold skew factor t qhs 0.3 4 ns dq - dqs hold, dqs to first dq to go non - valid, per access t qh t hp - t qhs ns data valid output window t dvw t qh - t dqsq ns dqs input high pulse width t dqsh 0.35 t ck dqs input low pulse width t dqsl 0 .35 t ck dqs falling edge to ck rising - setup time t dss 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 t ck dqs C t dqsq 0.2 4 ns dqs read preamble t rpre 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 t ck dqs write preamble t wpre 0.35 t ck dqs write preamble setup time t wpres 0 ns dqs write postamble t wpst 0.4 0.6 t ck positive dqs latching edge to associated clock edge t dqss - 0.25 + 0.25 t ck write command to firs t dqs latching transition wl - t dqss wl+ t dqss t ck address and control input pulse width ( for each input ) t ipw 0.6 t ck address and control input setup time t is 0. 4 ns
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland ddr2 sdram component electrical characteristics and recommended ac operati ng conditions (continued) (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300 - 555 parameter symbol min max unit address and control input hold time t ih 0. 4 ns cas# to cas# command delay t ccd 2 t ck active t o active (same bank) command period t rc 55 ns active bank a to active bank b command t rrd 7.5 ns active to read or write delay t rcd 15 ns four bank activate period t faw 37.5 ns active to precharge command t ras 4 0 70 t rtp 7.5 ns write recovery time t wr 15 ns auto precharge write recovery + precharge time t dal t wr + t rp ns internal write to read command delay t wtr 7.5 ns precharge command period t rp 15 ns precharge all co mmand period t rpa t rp + t ck ns load mode command cycle time t mrd 2 t ck cke low to ck, ck# uncertainty t delay t is + t ck + t ih t ck refresh to active or refresh to refresh command interval t rfc 195 70 (0c <= t case <= 85 c) t refi 7.8 s (85c<= t case <= 95 c) t refi (it) 3.9 exit self refresh to non - read command t xsnr t rfc (min) + 10 ns exit self refresh to read command t xsrd 200 t ck exit self refresh timing reference t isxr t is ps odt tu rn - on delay t aond 2 2 t ck odt turn - on t aon t ac (min) t ac (max) + 1,000 ps odt turn - off delay t aofd 2.5 2.5 t ck odt turn - off t aof t ac (min) t ac (max) + 600 ps odt turn - on (power - down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 ps od t turn - off (power - down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power - down entry latency t anpd 3 t ck
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland ddr2 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300 - 555 parameter symbol min max unit odt power - down exit latency t axpd 8 t ck odt enable from mrs command t mod 12 ns exit active power - down to read command, mr [bit 12 = 0] t xard 2 t ck exit active power - down to read command, mr [bit 12 = 1] t xards 7 C ck exit precharge power - down to any non - read command t xp 2 t ck cke minimum high/low time t cke 3 t ck register specifications parameter symb ol pins conditions min max units dc high - level input voltage v ih ( dc ) address, control, command sstl_18 v ref ( dc ) + 125 v dd q + 250 mv dc low - level input voltage v il ( dc ) address, control, command sstl_18 0 v ref ( dc ) - 125 mv ac high - level input voltage v ih ( ac ) address, control, command sstl_18 v ref ( dc ) + 250 v dd mv ac low - level input voltage v il ( ac ) address, control, command sstl_18 0 v ref ( dc ) - 250 mv output high voltage v oh parity output lvcmos 1.2 - v output low voltage v ol parity output lvcmos - 0.5 v input current i i all pins v i = v dd q or v ss q - 5 +5 a static standby i dd all pins reset# = v ss q (i o = 0) - 100 a static operating i dd all pins reset# = v ss q; v i = v ih ( ac ) or v il ( dc ) i o = 0 - 40 ma dynamic operating (clock tree) i ddd n/a reset# = v dd , v i = v ih ( ac ) or v il ( ac ), i o = 0; ck and ck# switching 50% duty cycle - varies by manufacturer a dynamic operating (per each input) i ddd n/a reset# = v dd , v i = v ih ( ac ) or v il ( ac ), i o = 0; ck and ck# switching 50% duty cycle; one data input switching at t c k/2 , 50% duty cycle - varies by manufacturer a input capacitance (per device, per pin) c i data v i = v ref 250mv; v dd q = 1.8v 2.5 3.5 pf input capacitance (per device, per pin) c i reset# v i = v dd q or v ss q - varies by manufacturer pf notes: 1. timing an d switching specifications for the register listed above are critical for proper operation of the ddr2 sdram registered dimms. these are meant to be a subset of the parameters for the specific device used on the module. detailed information for this regist er is available in jedec standard jesd82.
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland serial presence - detect matrix byte description 5300 - 555 0 number of spd bytes used 0x80 1 total number of bytes in spd device 0x 08 2 fundamental memory type 0x 08 3 number of row addresses on assembly 0x 0f 4 number of column addresses on assembly 0x 0a 5 dimm hight and module ranks 0x61 6 module data width 0x 48 7 reserved 0x 00 8 module voltage interface levels (v dd q) 0x 05 9 sdram cycle time, (t ck ) [max cl] cas latency = 5 (5300), cl = 4 (4200) 0x 30 1 0 sdram access from clock, (t ac ) [max cl] cas latency = 5 (5300); cl = 4 (4200) 0x 45 11 module configuration type 0x 02 12 refresh rate / type 0x 82 13 sdram device width (primary sdram) 0x 08 14 error - checking sdram data width 0x 08 15 minimum clock de lay, back - to - back random column access 0x 00 16 burst lengths supported 0x 0c 17 number of banks on sdram device 0x 08 18 cas latencies supported 0x 38 19 module thickness 0x 01 20 ddr2 dimm type 0x 07 21 sdram module attributes 0x 04 22 sdram device attri butes: weak driver and 50 ? odt 0x 03 23 sdram cycle time, (t ck ) [max cl C 1] cas latency = 4 (5300), cl = 3 (4200) 0x 3d 24 sdram access from ck, (t ac ) [max cl C 1] cas latency = 4 (5300), cl = 3 (4200) 0x45 25 sdram cycle time, (t ck ) [max cl C 2] cas la tency = 3 (5300) 0x 50 26 sdram access from ck, (t ac ) [max cl C 2] cas latency = 3 (5300) 0x 45 27 minimum row precharge time, (t rp ) 0x 3c 28 minimum row active to row active, (t rrd ) 0x 1e 29 minimum ras# to cas# delay, (t rcd ) 0x 3c 30 minimum ras# pulse w idth, (t ras ) 0x 2d 31 module bank density 0x02
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland serial presence - dtect matrix (continued) byte description 5300 - 555 32 address and command setup time, (t isb ) 0x 20 33 address and command hold time, (t ihb ) 0x27 34 data / data mask input setup time, (t d sb ) 0x 10 35 data / data mask input hold time, (t dhb ) 0x17 36 write recovery time, (t wr ) 0x 3c 37 write to read command delay, (t wtr ) 0x 1e 38 read to precharge command delay, (t rtp ) 0x 1e 39 mem analysis probe 0x 00 40 extension for bytes 41 and 42 0x00 41 min active auto refresh time, (t rc ) 0x 3 7 42 minimum auto refresh to active / auto refresh command period, (t rfc) 0x c3 43 sdram device max cycle time, (t ckmax ) 0x 80 44 sdram device max dqs - dq skew time, (t dqsq ) 0x 18 45 sdram device max read data ho ld skew factor, (t qhs ) 0x 22 46 pll relock time 0x 0f 47 - 61 optional features, not supported 0x 00 62 spd revision 0x 13 63 checksum for bytes 0 - 62 0x 53 64 - 66 manufacturer`s jedec id code 0x 7f 67 manufacturer`s jedec id code (continued) 0xda 68 - 71 manuf acturer`s jedec id code (continued) 0x 00 72 manufacturing location 0x02 73 - 90 module part number (ascii) seg04g72b1bc2mt - 30 91 pcb identification code x 92 identification code (continued) x 93 year of manufactu re in bcd x 94 week of manufacture in bcd x 95 - 98 module serial number x 99 - 127 manufacturer - specific data (rsvd) 0x00 128 - 255 open for customer use 0x ff part number code s e g 04g 72 b 1 b c 2 mt - 30 * r 1 2 3 4 5 6 7 8 9 10 11 12 13 *rohs compl. swissbit ag ddr2 - 667 m t/s sdram d dr 2 200 pin registered 1.8v chip vendor (micron) depth ( 4 gb) 2 module rank width chip rev. c pcb - type ( s2f3e - 100 ) chip organisation x 8
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland revision history revision changes date 0. 9 initial revision 07.01.2013 * optional / additional information
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 15 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland locations swissbit ag industriestrasse 4 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _____________________________ swissbit na, inc. 1202 e. winding creek drive eagle, id 83616 usa phone: +1 208 870 4525 fax: +1 208 870 4525 _____________________________ swissbit japan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, suginami - ku, tokyo 166 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512 _____________________________ ___
preliminary data sheet rev.0.9 07.01.2013 swissbit industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 16 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 switzerland declaration of conformity we manufacturer: swissbit ag industriestrasse 4 ch - 9552 bronschhofen switzerland declare under our sole responsibility that the product product type: so - rdimm brand name: swissmemory? product series: ddr2 - sordimm part number: seg04g72b1bc2mt - xxr to which this declaration relates is in conformity with the following directives: 2002/96/ec category 3 (weee) following the provisions of directive restric tion of the use of certain hazardous substances 2011/65/eu swissbit ag, januar 2013 manuela k?gel head of quality management

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